0 sats \ 1 reply \ @endothermicdev 10 Feb \ on: Hypothetical: programmable photonic chip efficiency match ASICs. wat mean 4 btc? bitcoin
First off, I love lateral thinking like this.
However, I don't understand how MEMS is supposed to help here. The lithography processes used for MEMS and those used for high efficiency ICs are quite different. I.e., the minimum feature size of MEMS is about 2um versus 4nm or something for ICs. If I understand you correctly, you want to move logic blocks around with a transport system that's ~1000x bigger? Wouldn't it be simpler and more efficient to just include both the SHA256 and the matrix multiplication on the same die as parallel processes and only use what you need? I think it would use less die space and still allow the flexibility to switch operations while using the rest of the infrastructure. Maybe I'm missing something.
I remember offhand something about photonic chips being something that can work well at the 100nm transistor size when I was looking at it a couple years ago, and that being an argument for greater decentralization since the fab costs would be much lower. I'm not sure what the size-efficiency relationship is like if you go past that.
My thought would also be parallel ASICs, shared power infrastructure would make more sense. Why do you save die space by having the two parallel systems be on the same chip?
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